Verilog Digital System Design: Register transfer level synthesis, testbench and verification (Record no. 2175)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 01282nam a22002297a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20190523152303.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 190523b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 978-0-07-025221-9 |
| 028 ## - PUBLISHER NUMBER | |
| Source | Allied Informatics, Jaipur |
| Bill Number | 6195 |
| Bill Date | 20/05/2019 |
| Purchase Year | 2019-20 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | BSDU |
| Language of cataloging | English |
| Transcribing agency | BSDU |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.392 |
| Item number | NAV |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Navabi, Zainalabedin |
| 245 ## - TITLE STATEMENT | |
| Title | Verilog Digital System Design: Register transfer level synthesis, testbench and verification |
| 250 ## - EDITION STATEMENT | |
| Remainder of edition statement | 2nd |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | Mcgraw Hill Education (India) Pvt. Ltd. |
| Date of publication, distribution, etc. | 2008; c2006 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 384 |
| 500 ## - GENERAL NOTE | |
| General note | This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Contents:<br/>1. Digital System Design Automation with Verilog<br/>2. Register Transfer Level Design with Verilog<br/>3. Verilog Language Concepts<br/>4. Combinational Circuit Description<br/>5. Sequential Circuit Description<br/>6.Component Test and Verification<br/>7. Detailed Modeling<br/>8. RT Level Design and Test<br/>Appendix<br/>Index |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Electronics |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Cost, normal purchase price | Total Checkouts | Full call number | Barcode | Date last seen | Cost, replacement price | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | BSDU Knowledge Resource Center, Jaipur | BSDU Knowledge Resource Center, Jaipur | General Stacks | 05/23/2019 | 695.00 | 621.392 NAV | 017769 | 02/12/2020 | 695.00 | 05/23/2019 | Books | |||||
| Dewey Decimal Classification | Not For Loan | BSDU Knowledge Resource Center, Jaipur | BSDU Knowledge Resource Center, Jaipur | General Stacks | 05/23/2019 | 695.00 | 621.392 NAV | CD848 | 05/23/2019 | 695.00 | 05/23/2019 | CDs & DVDs |