Verilog HDL Design Examples (Record no. 2212)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01882nam a22002177a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20190530102845.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 190530b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 978-1-138-09995-1 |
| 028 ## - PUBLISHER NUMBER | |
| Source | Allied Informatics, Jaipur |
| Bill Number | 6218 |
| Bill Date | 29/05/2019 |
| Purchase Year | 2019-20 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | BSDU |
| Language of cataloging | English |
| Transcribing agency | BSDU |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.381 |
| Item number | CAV |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Cavanagh, Joseph |
| 245 ## - TITLE STATEMENT | |
| Title | Verilog HDL Design Examples |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | London |
| Name of publisher, distributor, etc. | CRC Press |
| Date of publication, distribution, etc. | c2018 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 655 |
| 500 ## - GENERAL NOTE | |
| General note | The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles—including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs). |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Contents<br/>Preface<br/><br/>Chapter 1 Introduction to Logic Design Using Verilog HDL<br/><br/>1.1 Language Elements<br/><br/>1.2 Expressions<br/><br/>1.3 Modules and Ports<br/><br/>1.4 Built-In Primitives<br/><br/>1.5 User-Defined Primitives<br/><br/>1.6 Dataflow Modeling<br/><br/>1.7 Behavioral Modeling<br/><br/>1.8 Structural Modeling<br/><br/>1.9 Tasks and Functions |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Electrical |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Collection code | Home library | Current library | Date acquired | Cost, normal purchase price | Total Checkouts | Full call number | Barcode | Date last seen | Cost, replacement price | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | Not For Loan | Reference | BSDU Knowledge Resource Center, Jaipur | BSDU Knowledge Resource Center, Jaipur | 05/30/2019 | 12744.00 | 621.381 CAV | 017777 | 02/12/2020 | 12744.00 | 05/30/2019 | Books |