<?xml version="1.0" encoding="UTF-8"?>
<mods xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://www.loc.gov/mods/v3" version="3.1" xsi:schemaLocation="http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-1.xsd">
  <titleInfo>
    <title>Algorithms for VLSI Design Automation</title>
  </titleInfo>
  <name type="personal">
    <namePart>Gerez, Sabih H.</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
    </role>
  </name>
  <typeOfResource>text</typeOfResource>
  <originInfo>
    <place>
      <placeTerm type="code" authority="marccountry">xx</placeTerm>
    </place>
    <place>
      <placeTerm type="text">New Delhi</placeTerm>
    </place>
    <publisher>Wiley India Pvt. Ltd. India</publisher>
    <dateIssued>2013,c1999</dateIssued>
    <dateIssued encoding="marc">9999</dateIssued>
    <edition>2nd</edition>
    <issuance>monographic</issuance>
  </originInfo>
  <language>
    <languageTerm authority="iso639-2b" type="code">und</languageTerm>
  </language>
  <physicalDescription>
    <form authority="marcform">print</form>
    <extent>326</extent>
  </physicalDescription>
  <note>Enrollments in VLSI design automation courses are not large but it's a very popular elective, especially for those seeking a career in the microelectronics industry. Already the reviewers seem very enthusiastic about the coverage of the book being a better match for their courses than available competitors, because it covers all design phases. It has plenty of worked problems and a large no. of illustrations. It's a good 'list-builder' title that matches our strategy of focusing on topics that lie on the interface between Elec Eng and Computer Science.

 </note>
  <note>TABLE OF CONTENTS
Preliminaries

·	Introduction to Design Methodologies

·	A Quick Tour of VLSI Design Automation Tools

·	Algorithmic Graph Theory and Computational Complexity

·	Tractable and Intractable Problems

·	General-purpose Methods for Combinatorial Optimization

Selected Design Problems And Algorithms

·	Layout Compaction

·	Placement and Partitioning

·	Floor planning

·	Routing

·	Simulation

·	Logic Synthesis and Verification

·	High-level Synthesis
</note>
  <subject>
    <topic>Electronics</topic>
  </subject>
  <classification authority="ddc">621.395  GER</classification>
  <identifier type="isbn">9788126508211</identifier>
  <identifier type="">Allied Informatics, Jaipur</identifier>
  <recordInfo>
    <recordContentSource authority="marcorg">BSDU</recordContentSource>
    <recordCreationDate encoding="marc">170602</recordCreationDate>
    <recordChangeDate encoding="iso8601">20190306140305.0</recordChangeDate>
    <recordIdentifier source="OSt">0000038</recordIdentifier>
    <languageOfCataloging>
      <languageTerm authority="iso639-2b" type="code">English</languageTerm>
    </languageOfCataloging>
  </recordInfo>
</mods>
