01282nam a22002297a 4500 2175 2175 OSt 20190523152303.0 190523b ||||| |||| 00| 0 eng d 978-0-07-025221-9 Allied Informatics, Jaipur 6195 20/05/2019 2019-20 BSDU English BSDU 621.392 NAV Navabi, Zainalabedin Verilog Digital System Design: Register transfer level synthesis, testbench and verification 2nd New Delhi Mcgraw Hill Education (India) Pvt. Ltd. 2008; c2006 384 This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library. Contents: 1. Digital System Design Automation with Verilog 2. Register Transfer Level Design with Verilog 3. Verilog Language Concepts 4. Combinational Circuit Description 5. Sequential Circuit Description 6.Component Test and Verification 7. Detailed Modeling 8. RT Level Design and Test Appendix Index Electronics ddc BK 0 0 ddc 0 0 BSDU BSDU GEN 2019-05-23 695.00 0 621.392 NAV 017769 2020-02-12 00:00:00 695.00 2019-05-23 BK 0 0 ddc 0 1 BSDU BSDU GEN 2019-05-23 695.00 0 621.392 NAV CD848 2019-05-23 00:00:00 695.00 2019-05-23 CD