Verilog Digital System Design: Register transfer level synthesis, testbench and verification

Verilog Digital System Design: Register transfer level synthesis, testbench and verification Navabi, Zainalabedin creator text New Delhi Mcgraw Hill Education (India) Pvt. Ltd. 2008; c2006 monographic eng 384 This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library. Contents: 1. Digital System Design Automation with Verilog 2. Register Transfer Level Design with Verilog 3. Verilog Language Concepts 4. Combinational Circuit Description 5. Sequential Circuit Description 6.Component Test and Verification 7. Detailed Modeling 8. RT Level Design and Test Appendix Index Electronics 621.392 NAV 978-0-07-025221-9 Allied Informatics, Jaipur BSDU 190523 20190523152303.0 English