<?xml version="1.0" encoding="UTF-8"?>
<record
    xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
    xsi:schemaLocation="http://www.loc.gov/MARC21/slim http://www.loc.gov/standards/marcxml/schema/MARC21slim.xsd"
    xmlns="http://www.loc.gov/MARC21/slim">

  <leader>02320nam a22002417a 4500</leader>
  <datafield tag="999" ind1=" " ind2=" ">
    <subfield code="c">2177</subfield>
    <subfield code="d">2177</subfield>
  </datafield>
  <controlfield tag="003">OSt</controlfield>
  <controlfield tag="005">20190523154350.0</controlfield>
  <controlfield tag="008">190523b           ||||| |||| 00| 0 eng d</controlfield>
  <datafield tag="020" ind1=" " ind2=" ">
    <subfield code="a">978-1-25-902597-6</subfield>
  </datafield>
  <datafield tag="028" ind1=" " ind2=" ">
    <subfield code="b">Allied Informatics, Jaipur</subfield>
    <subfield code="c">6195</subfield>
    <subfield code="d">20/05/2019</subfield>
    <subfield code="q">2019-20</subfield>
  </datafield>
  <datafield tag="040" ind1=" " ind2=" ">
    <subfield code="a">BSDU</subfield>
    <subfield code="b">English</subfield>
    <subfield code="c">BSDU</subfield>
  </datafield>
  <datafield tag="082" ind1=" " ind2=" ">
    <subfield code="a">621.395</subfield>
    <subfield code="b">BRO</subfield>
  </datafield>
  <datafield tag="100" ind1=" " ind2=" ">
    <subfield code="a">Brown, Stephen </subfield>
  </datafield>
  <datafield tag="245" ind1=" " ind2=" ">
    <subfield code="a">Fundamentals of Digital Logic with VHDL Design</subfield>
  </datafield>
  <datafield tag="250" ind1=" " ind2=" ">
    <subfield code="b">3rd </subfield>
  </datafield>
  <datafield tag="260" ind1=" " ind2=" ">
    <subfield code="a">Chennai</subfield>
    <subfield code="b">Mcgraw Hill Education (India) Pvt. Ltd.</subfield>
    <subfield code="c">2012; c2009</subfield>
  </datafield>
  <datafield tag="300" ind1=" " ind2=" ">
    <subfield code="a">939</subfield>
  </datafield>
  <datafield tag="500" ind1=" " ind2=" ">
    <subfield code="a">Fundamentals of Digital Logic with VHDL Design teaches the basic design techniques for logic circuits. The text ptovides a clear and easily understandable discussion of logic circuit design without the use of unnecessary formalism. It emphasizes the synthesis of circuits and explains how circuits are implemented in real chips. Fundamental concepts are illustrated by using small examples, which are easy to understand. Then, a modular approach is used to show how larger circuits are designed.
VHDL is a complex language so it is introduced gradually in the book. Each VHDL feature is presented as it becomes pertinent for the circuits being discussed. While it includes a discussion of VHDL, the book provides thorough coverage of the fundamental concepts of logic circuit design, independent of the use of VHDL and CAD tools. A CD-ROM containg all of the VHDL design examples used in the book, as well Altera's Quartus II CAD software, is included free with every text.</subfield>
  </datafield>
  <datafield tag="504" ind1=" " ind2=" ">
    <subfield code="a">Contents
1 Design Concepts 
2 Introduction to Logic Circuits
 3 Implementation Technology
 4 Optimized Implementation of Logic Functions 
5 Number Representation and Arithmetic Circuits 
6 Combinational-Circuit Building Blocks 
7 Flip-Flops, Registers, Counters, and a Simple Processor 
8 Synchronous Sequential Circuits 
9 Asynchronous Sequential Circuits 
10 Digital System Design
 11 Testing of Logic Circuits 
12 Computer Aided Design Tools 
Appendix A VHDL Reference 
Appendix B Tutorial 1 - Using Quartus II CAD Software Appendix C Tutorial 2 - Implementing Circuits in Altera Devices 
Appendix D Tutorial 3 - Using Quartus II Tools
 Appendix E Commercial Devices Answers</subfield>
  </datafield>
  <datafield tag="650" ind1=" " ind2=" ">
    <subfield code="a">Electronics</subfield>
  </datafield>
  <datafield tag="700" ind1=" " ind2=" ">
    <subfield code="a">Vranesic, Zvonko</subfield>
  </datafield>
  <datafield tag="942" ind1=" " ind2=" ">
    <subfield code="2">ddc</subfield>
    <subfield code="c">BK</subfield>
  </datafield>
  <datafield tag="952" ind1=" " ind2=" ">
    <subfield code="0">0</subfield>
    <subfield code="1">0</subfield>
    <subfield code="2">ddc</subfield>
    <subfield code="4">0</subfield>
    <subfield code="7">0</subfield>
    <subfield code="a">BSDU</subfield>
    <subfield code="b">BSDU</subfield>
    <subfield code="c">GEN</subfield>
    <subfield code="d">2019-05-23</subfield>
    <subfield code="g">900.00</subfield>
    <subfield code="l">0</subfield>
    <subfield code="o">621.395 BRO</subfield>
    <subfield code="p">017771</subfield>
    <subfield code="r">2020-02-12 00:00:00</subfield>
    <subfield code="v">900.00</subfield>
    <subfield code="w">2019-05-23</subfield>
    <subfield code="y">BK</subfield>
  </datafield>
  <datafield tag="952" ind1=" " ind2=" ">
    <subfield code="0">0</subfield>
    <subfield code="1">0</subfield>
    <subfield code="2">ddc</subfield>
    <subfield code="4">0</subfield>
    <subfield code="7">1</subfield>
    <subfield code="a">BSDU</subfield>
    <subfield code="b">BSDU</subfield>
    <subfield code="d">2019-05-23</subfield>
    <subfield code="g">900.00</subfield>
    <subfield code="l">0</subfield>
    <subfield code="o">621.395 BRO</subfield>
    <subfield code="p">CD849</subfield>
    <subfield code="r">2019-05-23 00:00:00</subfield>
    <subfield code="v">900.00</subfield>
    <subfield code="w">2019-05-23</subfield>
    <subfield code="y">CD</subfield>
  </datafield>
</record>
