01882nam a22002177a 4500 2212 2212 OSt 20190530102845.0 190530b ||||| |||| 00| 0 eng d 978-1-138-09995-1 Allied Informatics, Jaipur 6218 29/05/2019 2019-20 BSDU English BSDU 621.381 CAV Cavanagh, Joseph Verilog HDL Design Examples London CRC Press c2018 655 The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles—including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs). Contents Preface Chapter 1 Introduction to Logic Design Using Verilog HDL 1.1 Language Elements 1.2 Expressions 1.3 Modules and Ports 1.4 Built-In Primitives 1.5 User-Defined Primitives 1.6 Dataflow Modeling 1.7 Behavioral Modeling 1.8 Structural Modeling 1.9 Tasks and Functions Electrical ddc BK 0 0 ddc 0 1 REF BSDU BSDU 2019-05-30 12744.00 0 621.381 CAV 017777 2020-02-12 00:00:00 12744.00 2019-05-30 BK