02003nam a22002297a 4500999001500000003000400015005001700019008004100036020002200077028005800099040002400157082001700181100002100198245003200219260002900251300000800280500103400288504029401322650001501616942001201631952013001643  c2212d2212OSt20190530102845.0190530b           ||||| |||| 00| 0 eng d  a978-1-138-09995-1  bAllied Informatics, Jaipurc6218d29/05/2019q2019-20  aBSDUbEnglishcBSDU  a621.381bCAV  aCavanagh, Joseph  aVerilog HDL Design Examples  aLondonbCRC Presscc2018  a655  aThe Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles—including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs).  aContents
Preface

Chapter 1 Introduction to Logic Design Using Verilog HDL

1.1 Language Elements

1.2 Expressions

1.3 Modules and Ports

1.4 Built-In Primitives

1.5 User-Defined Primitives

1.6 Dataflow Modeling

1.7 Behavioral Modeling

1.8 Structural Modeling

1.9 Tasks and Functions  aElectrical  2ddccBK  00102ddc40718REFaBSDUbBSDUd2019-05-30g12744.00l0o621.381 CAVp017777r2020-02-12 00:00:00v12744.00w2019-05-30yBK