01317nam a22002417a 4500 2386 2386 OSt 20191011121007.0 191011b ||||| |||| 00| 0 eng d 978-613-9-45302-3 Lambert Academic Publishing R242311 25/09/2019 2019-20 BSDU English BSDU 621.3 SIN Singar, Sumitra Low Power Fault Tolerant Latches and Flip-flops: Design and performance analysis Mauritius Lambert Academic Publishing 2018 128 This book focus on review, study and design of fault tolerant circuits to reduce circuit-level faults and protect a circuit from faults. In this book eight novel low power fault tolerant latches and four glitch free flip-flops are discussed. The latch configurations are designed with the 1P-2N structure and 2P-1N structure or 1P-2N structure, 2P-1N structure and C-element structure. Contents Introduction Existing Fault Tolerant Latches and Flip-Flops Fault Free D-Latch Configurations Robust Fault Resistant D-Latch Glitch Free Novel Det Flip-Flop Near & Super Threshold Regions Impact on Power and Delay Conclusions Electrical Ghosh, Pradip Kumar Joshi, Narendra Kumar ddc BK 0 0 ddc 0 1 REF BSDU BSDU 2019-10-11 4842.43 0 621.3 SIN 017931 2020-02-12 00:00:00 4842.43 2019-10-11 BK