TY  - BOOK
AU  - Singar, Sumitra
AU  - Ghosh, Pradip Kumar
AU  - Joshi, Narendra Kumar
TI  - Low Power Fault Tolerant Latches and Flip-flops: Design and performance analysis
SN  - 978-613-9-45302-3
U1  - 621.3 
PY  - 2018///
CY  - Mauritius
PB  - Lambert Academic Publishing
KW  - Electrical
N1  - This book focus on review, study and design of fault tolerant circuits to reduce circuit-level faults and protect a circuit from faults. In this book eight novel low power fault tolerant latches and four glitch free flip-flops are discussed. The latch configurations are designed with the 1P-2N structure and 2P-1N structure or 1P-2N structure, 2P-1N structure and C-element structure; Contents
Introduction
Existing Fault Tolerant Latches and Flip-Flops
Fault Free D-Latch Configurations
Robust Fault Resistant D-Latch
Glitch Free Novel Det Flip-Flop
Near & Super Threshold Regions Impact on Power and Delay
Conclusions
ER  -