02066nam a2200229Ia 45000010008000000030004000080050017000120080041000290200018000700280037000880400024001250820021001491000022001702450054001922500009002462600056002553000008003115000795003195040682011146500016017967000024018120002168OSt20190318134034.0170602s9999    xx            000 0 und d  a9788126520312  q2016bAllied Informatics, Jaipur  bEnglishaBSDUcBSDU  a621.381 527bHIL  aHill, Fredrick J  0aIntroduction to Switching Theory & Logical Design  a3rd   bWiley India Pvt. Ltd. Indiaa New Delhic2011,c1981  a617  aIn this edition, author provides revised and updated information on AHPL. Two programs namely a functional level simulator and a hardware compiler have been added in this textbook to support AHPL. The language used in Chapters 11 and 12 to describe hardware is completely consistent with the AHPL of the previous edition. Chapter 9 has been expanded to provide more through coverage of various types of flip-flops. Chapter 3 and 4 provide the basic logical and algebraic basis for switching theory. Chapter 5 has been rewritten to reflect recent innovations in digital circuit design. The important topic of programmed logic arrays (PLAs) has been added to Chapter 8. The chapter on level mode analysis and synthesis has been improved and extended to include the edge-triggered D flip-flop.  aContents
	Introduction

·	Number Systems

·	Truth Functions

·	Boolean Algebra

·	Switching Devices

·	Minimization of Boolean Functions

·	Tabular Minimization and Multiple-Output Circuits

·	Special Realization and Codes

·	Introduction to Sequential Circuits

·	Synthesis of Clock-Mode Sequential Circuits

·	Clock-Control and Pulse-Mode Circuits

·	Logical Design Using MSI and LSI Parts

·	Incompletely Specified Sequential Circuits

·	Level-Mode Sequential Circuits

·	A Second Look at Flip-Flops and Timings

·	Combinational Functions with Special Properties

Appendix A

Selection of Minimal Closed Covers

Bibliography

Appendix B

Relay Circuits

Index  aElectronics  a Peterson, Gerald R