01487nam a2200217Ia 45000010008000000030004000080050017000120080041000290200018000700280037000880400024001250820018001491000016001672450016001832500008001992600040002073000008002475000372002555040626006276500016012530000015OSt20190225132140.0170602s9999 xx 000 0 und d a9789332557161 q2016bAllied Informatics, Jaipur bEnglishaBSDUcBSDU a621.392 bBHA aBhaskar, J. 0aVHDL Primer a3rd bPearson Educationa New Delhic2016 a395 aThis book introduces the VHDL language to the reader at the beginner's level. It presents a subset of VHDL consisting of commonly used features that make it both simple and easy to use. The extensive hardware modeling coverage includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers and much more. aTable of Content Chapter 1 Introduction Chapter 2 A Tutorial Chapter 3 Basic Language Elements Chapter 4 Behavioral Modeling Chapter 5 Dataflow Modeling Chapter 6 Structural Modeling Chapter 7 Generics and Configurations Chapter 8 Subprograms and Overloading Chapter 9 Packages and Libraries Chapter 10 Advanced Features Chapter 11 Model Simulation Chapter 12 Hardware Modeling Examples Appendix A Predefined Environment Appendix B Syntax Reference Appendix C A Package Example Appendix D Summary of Changes Appendix E The STD_LOGIC_1164 Package Appendix F An Utility Package Appendix G Solved Questions aElectronics