01508nam a2200241Ia 4500 602 602 0002310 OSt 20190326124603.0 170602s9999 xx 000 0 und d 9788126519316 2016 Allied Informatics, Jaipur English BSDU BSDU 621.392 PAD Padmanabhan, T R Design Through Verilog HDL Wiley India Pvt. Ltd. India New Delhi 2015,c2004 455 If you aspire to master Verilog language and become a competent EDA professional, this book is for you. It fills the need for an elaborate construct in Verilog, and clarifies their implications, illustrating their need and utility. This is especially true fo the latest IEEE Standard 1364 for Verilog. Contents Preface Acknowledgements · Introduction to VLSI Design · Introduction to Verilog · Language Constructs and Conventions in Verilog · Gate Level Modeling - 1 · Gate Level Modeling - 2 · Modeling at Data Flow Level · Behavioral Modeling - 1 · Behavioral Modeling II · Functions, Tasks, and User-Defined Primitives · Switch Level Modeling 305 · System Tasks, Functions, and Compiler Directives 339 · Queues, PLAS, and FSMS Appendix A (Keywords and Their Significance) Appendix B (Truth Tables of Gates and Switches) References Index Electronics Sundrai, B Bala Tripura ddc BK 0 0 ddc 0 0 BSDU BSDU 2016-12-12 599.00 0 621.392 PAD 002310 2020-02-12 00:00:00 599.00 2017-06-02 BK 0 0 ddc 0 0 BSDU BSDU 2016-12-12 599.00 0 621.392 PAD 002311 2020-02-12 00:00:00 599.00 2017-06-02 BK 0 0 ddc 0 1 RB BSDU BSDU 2016-12-12 599.00 0 621.392 PAD 002312 2020-02-12 00:00:00 599.00 2017-06-02 BK