01879nam a2200277Ia 4500999001300000001000800013003000400021005001700025008004100042020001800083028003700101040002400138082001800162100002200180245003100202260005600233300000800289500030600297504057100603650001601174700002901190942001201219952012201231952012201353952012601475 c602d6020002310OSt20190326124603.0170602s9999 xx 000 0 und d a9788126519316 q2016bAllied Informatics, Jaipur bEnglishaBSDUcBSDU a621.392 bPAD aPadmanabhan, T R  0aDesign Through Verilog HDL bWiley India Pvt. Ltd. Indiaa New Delhic2015,c2004 a455 aIf you aspire to master Verilog language and become a competent EDA professional, this book is for you. It fills the need for an elaborate construct in Verilog, and clarifies their implications, illustrating their need and utility. This is especially true fo the latest IEEE Standard 1364 for Verilog. aContents Preface Acknowledgements · Introduction to VLSI Design · Introduction to Verilog · Language Constructs and Conventions in Verilog · Gate Level Modeling - 1 · Gate Level Modeling - 2 · Modeling at Data Flow Level · Behavioral Modeling - 1 · Behavioral Modeling II · Functions, Tasks, and User-Defined Primitives · Switch Level Modeling 305 · System Tasks, Functions, and Compiler Directives 339 · Queues, PLAS, and FSMS Appendix A (Keywords and Their Significance) Appendix B (Truth Tables of Gates and Switches) References Index aElectronics a Sundrai, B Bala Tripura 2ddccBK 00102ddc4070aBSDUbBSDUd2016-12-12g599.00l0o621.392 PADp002310r2020-02-12 00:00:00v599.00w2017-06-02yBK 00102ddc4070aBSDUbBSDUd2016-12-12g599.00l0o621.392 PADp002311r2020-02-12 00:00:00v599.00w2017-06-02yBK 00102ddc40718RBaBSDUbBSDUd2016-12-12g599.00l0o621.392 PADp002312r2020-02-12 00:00:00v599.00w2017-06-02yBK