Low Power Fault Tolerant Latches and Flip-flops: Design and performance analysis

By:

Singar, Sumitra

Contributor(s):

Material type:

TextPublisher number: Lambert Academic Publishing | 2019-20Publication details: Mauritius Lambert Academic Publishing 2018Description: 128ISBN:

978-613-9-45302-3

Subject(s):

Electrical

DDC classification:

621.3 SIN

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Holdings
Item type	Current library	Collection	Call number	Status	Barcode
Books	BSDU Knowledge Resource Center, Jaipur	Reference	621.3 SIN (Browse shelf(Opens below))	Not For Loan	017931

This book focus on review, study and design of fault tolerant circuits to reduce circuit-level faults and protect a circuit from faults. In this book eight novel low power fault tolerant latches and four glitch free flip-flops are discussed. The latch configurations are designed with the 1P-2N structure and 2P-1N structure or 1P-2N structure, 2P-1N structure and C-element structure.

Contents
Introduction
Existing Fault Tolerant Latches and Flip-Flops
Fault Free D-Latch Configurations
Robust Fault Resistant D-Latch
Glitch Free Novel Det Flip-Flop
Near & Super Threshold Regions Impact on Power and Delay
Conclusions

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