000			01882nam a22002177a 4500
999			_c2212 _d2212
003			OSt
005			20190530102845.0
008			190530b ||||| |||| 00| 0 eng d
020			_a978-1-138-09995-1
028			_bAllied Informatics, Jaipur _c6218 _d29/05/2019 _q2019-20
040			_aBSDU _bEnglish _cBSDU
082			_a621.381 _bCAV
100			_aCavanagh, Joseph
245			_aVerilog HDL Design Examples
260			_aLondon _bCRC Press _cc2018
300			_a655
500			_aThe Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles—including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs).
504			_aContents Preface Chapter 1 Introduction to Logic Design Using Verilog HDL 1.1 Language Elements 1.2 Expressions 1.3 Modules and Ports 1.4 Built-In Primitives 1.5 User-Defined Primitives 1.6 Dataflow Modeling 1.7 Behavioral Modeling 1.8 Structural Modeling 1.9 Tasks and Functions
650			_aElectrical
942			_2ddc _cBK