000			01317nam a22002417a 4500
999			_c2386 _d2386
003			OSt
005			20191011121007.0
008			191011b ||||| |||| 00| 0 eng d
020			_a978-613-9-45302-3
028			_bLambert Academic Publishing _cR242311 _d25/09/2019 _q2019-20
040			_aBSDU _bEnglish _cBSDU
082			_a621.3 _bSIN
100			_aSingar, Sumitra
245			_aLow Power Fault Tolerant Latches and Flip-flops: Design and performance analysis
260			_aMauritius _bLambert Academic Publishing _c2018
300			_a128
500			_aThis book focus on review, study and design of fault tolerant circuits to reduce circuit-level faults and protect a circuit from faults. In this book eight novel low power fault tolerant latches and four glitch free flip-flops are discussed. The latch configurations are designed with the 1P-2N structure and 2P-1N structure or 1P-2N structure, 2P-1N structure and C-element structure.
504			_aContents Introduction Existing Fault Tolerant Latches and Flip-Flops Fault Free D-Latch Configurations Robust Fault Resistant D-Latch Glitch Free Novel Det Flip-Flop Near & Super Threshold Regions Impact on Power and Delay Conclusions
650			_aElectrical
700			_aGhosh, Pradip Kumar
700			_aJoshi, Narendra Kumar
942			_2ddc _cBK