000			01569nam a2200241Ia 4500
999			_c6 _d6
001			0000015
003			OSt
005			20190225132140.0
008			170602s9999 xx 000 0 und d
020			_a9789332557161
028			_q2016 _bAllied Informatics, Jaipur
040			_bEnglish _aBSDU _cBSDU
082			_a621.392 _bBHA
100			_aBhaskar, J.
245		0	_aVHDL Primer
250			_a3rd
260			_bPearson Education _a New Delhi _c2016
300			_a395
500			_aThis book introduces the VHDL language to the reader at the beginner's level. It presents a subset of VHDL consisting of commonly used features that make it both simple and easy to use. The extensive hardware modeling coverage includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers and much more.
504			_aTable of Content Chapter 1 Introduction Chapter 2 A Tutorial Chapter 3 Basic Language Elements Chapter 4 Behavioral Modeling Chapter 5 Dataflow Modeling Chapter 6 Structural Modeling Chapter 7 Generics and Configurations Chapter 8 Subprograms and Overloading Chapter 9 Packages and Libraries Chapter 10 Advanced Features Chapter 11 Model Simulation Chapter 12 Hardware Modeling Examples Appendix A Predefined Environment Appendix B Syntax Reference Appendix C A Package Example Appendix D Summary of Changes Appendix E The STD_LOGIC_1164 Package Appendix F An Utility Package Appendix G Solved Questions
650			_aElectronics
942			_2ddc _cBK