000			01508nam a2200241Ia 4500
999			_c602 _d602
001			0002310
003			OSt
005			20190326124603.0
008			170602s9999 xx 000 0 und d
020			_a9788126519316
028			_q2016 _bAllied Informatics, Jaipur
040			_bEnglish _aBSDU _cBSDU
082			_a621.392 _bPAD
100			_aPadmanabhan, T R
245		0	_aDesign Through Verilog HDL
260			_bWiley India Pvt. Ltd. India _a New Delhi _c2015,c2004
300			_a455
500			_aIf you aspire to master Verilog language and become a competent EDA professional, this book is for you. It fills the need for an elaborate construct in Verilog, and clarifies their implications, illustrating their need and utility. This is especially true fo the latest IEEE Standard 1364 for Verilog.
504			_aContents Preface Acknowledgements · Introduction to VLSI Design · Introduction to Verilog · Language Constructs and Conventions in Verilog · Gate Level Modeling - 1 · Gate Level Modeling - 2 · Modeling at Data Flow Level · Behavioral Modeling - 1 · Behavioral Modeling II · Functions, Tasks, and User-Defined Primitives · Switch Level Modeling 305 · System Tasks, Functions, and Compiler Directives 339 · Queues, PLAS, and FSMS Appendix A (Keywords and Their Significance) Appendix B (Truth Tables of Gates and Switches) References Index
650			_aElectronics
700			_a Sundrai, B Bala Tripura
942			_2ddc _cBK