Verilog Digital System Design: Register transfer level synthesis, testbench and verification
Material type:
TextPublisher number: Allied Informatics, Jaipur | 2019-20Publication details: New Delhi Mcgraw Hill Education (India) Pvt. Ltd. 2008; c2006Edition: 2ndDescription: 384ISBN: - 978-0-07-025221-9
- 621.392 NAV
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BSDU Knowledge Resource Center, Jaipur General Stacks | 621.392 NAV (Browse shelf(Opens below)) | Not For Loan | CD848 |
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| 621.384 SMI 3G Wireless Networks | 621.3897 BAL Consumer Electronics | 621.392 KAU VHDL: Basics to Programming | 621.392 NAV Verilog Digital System Design: Register transfer level synthesis, testbench and verification | 621.392 NAV Verilog Digital System Design: Register transfer level synthesis, testbench and verification | 621.392 ROT Digital Systems Design Using Verilog | 621.395 BRO Fundamentals of Digital Logic with VHDL Design |
This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library.
Contents:
1. Digital System Design Automation with Verilog
2. Register Transfer Level Design with Verilog
3. Verilog Language Concepts
4. Combinational Circuit Description
5. Sequential Circuit Description
6.Component Test and Verification
7. Detailed Modeling
8. RT Level Design and Test
Appendix
Index
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