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VLSI Design

By: Material type: TextPublisher number: Allied Informatics, Jaipur | 2019-20Publication details: New Delhi Oxford University Press 2015Edition: 2ndDescription: 626ISBN:
  • 978-0-19-809486-8
Subject(s): DDC classification:
  • 621.395 DAS
Summary: Features All the steps of VLSI design have been incorporated keeping in mind the industry perspective Terminologies used exclusively in the real design process are followed throughout the book Connection between VLSI design and CAD tools is also drawn in this book Different state-of-the-art electronic design automation (EDA) tools have been explained in detail Numerous review questions and unsolved problems provided as end-chapter exercises to help readers assess their understanding of the concepts discussed New to the Second Edition Chapters on MOS inverters, sub-system design, semiconductor memories, and low power logic circuits Sections on resonant tunnelling diodes, single electron transistors, spin transistors, ballistic electron devices, organic field effect transistors, carbon nanotubes, molecular transistors, small signal analysis of single-stage amplifiers, working principle of bistable circuits, and design of CMOS D flip-flops Revised and expanded coverage of topics such as PLD, Elmore delay model, Domino and NORA CMOS logic, and gate and device sizing
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Books BSDU Knowledge Resource Center, Jaipur General Stacks 621.395 DAS (Browse shelf(Opens below)) Available 017772

This second edition of VLSI Design is a comprehensive textbook designed for undergraduate students of electrical, electronics, and electronics and communication engineering. It provides a thorough understanding of the fundamental concepts and design of VLSI systems.

Beginning with an introduction to VLSI systems and basic concepts of MOS transistors, the book then proceeds to describe the various concepts of VLSI, such as the structure and operation of MOS transistors and inverters, standard cell library design and its characterization, analog and digital CMOS logic design, semiconductor memories, and BiCMOS technology and circuits. It then provides an exhaustive step-wise discussion of the various stages involved in designing a VLSI chip (which includes logic synthesis, timing analysis, floor planning, placement and routing, verification, and testing). In addition, the book includes chapters on FPGA architecture, VLSI process technology, subsystem design, and low-power logic circuits.

Contents
Chapter 1: Introduction to VLSI Systems
Chapter 2: MOS Transistors
Chapter 3: MOS Inverters
Chapter 4: Standard Cell Library Design and Characterization
Chapter 5: Analog CMOS Design
Chapter 6: Digital CMOS Logic Design
Chapter 7: Semiconductor Memories
Chapter 8: BiCMOS Technology and Circuits
Chapter 9: Logic Synthesis
Chapter 10: Timing Analysis
Chapter 11: Physical Design—Floorplanning, Placement, and Routing
Chapter 12: Verification and Reliability Analysis
Chapter 13: IC Packaging
Chapter 14: VLSI Testing
Chapter 15: Field Programmable Gate Array
Chapter 16: VLSI Process Technology
Chapter 17: Subsystem Design
Chapter 18: Low Power Logic Circuits

Features

All the steps of VLSI design have been incorporated keeping in mind the industry perspective
Terminologies used exclusively in the real design process are followed throughout the book
Connection between VLSI design and CAD tools is also drawn in this book
Different state-of-the-art electronic design automation (EDA) tools have been explained in detail
Numerous review questions and unsolved problems provided as end-chapter exercises to help readers assess their understanding of the concepts discussed
New to the Second Edition
Chapters on MOS inverters, sub-system design, semiconductor memories, and low power logic circuits
Sections on resonant tunnelling diodes, single electron transistors, spin transistors, ballistic electron devices, organic field effect transistors, carbon nanotubes, molecular transistors, small signal analysis of single-stage amplifiers, working principle of bistable circuits, and design of CMOS D flip-flops
Revised and expanded coverage of topics such as PLD, Elmore delay model, Domino and NORA CMOS logic, and gate and device sizing

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